The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particular to a method of fabricating CMOS devices having at least one metal silicide contact in which high temperature agglomeration of the same, typically caused during source/drain activation, is substantially eliminated. The present invention also provides CMOS structures having non-agglomerated metal silicide contacts prepared by the inventive process.
In current CMOS technology, metal silicide contacts are formed by a self-aligned process after the devices of the structure have been completed. The temperature necessary for silicide formation is high enough to significantly affect the dopant distribution in devices with shallow p-n junctions. The silicide anneals are also of sufficient duration to cause potential deactivation of dopants whose concentration is higher than the solubility limit at the siliciding annealing temperatures, leading to higher source/drain resistance.
In order to keep the dopant profile as tight as possible and avoid possible dopant deactivation, it would be advantageous to form the silicide before the dopants are implanted into the substrate. The disadvantage of the order of the processing steps is that if the silicide is formed before dopant implantation, the silicide needs to withstand the high temperature anneal (temperature of about 900xc2x0 C. or above) necessary for activating the implanted dopants. At these high temperatures, the electrical characteristics of the silicides in logic devices are severely degraded by the agglomeration of the silicide film.
One alternative to the above problem is to increase the thickness of the silicide film. If the dopant implantation occurs after silicide formation, the larger consumption of the silicon does not affect the junction depth as in current prior art processes. However, a thicker silicide film requires a deeper junction and has the disadvantage that increased diffusion during formation may cause stresses in the structure and slight changes in the effective dimensions.
In view of the above mentioned drawbacks with prior art methods of fabricating metal silicide contacts, there is a continued need for developing a new and improved method wherein silicide contacts can be fabricated without causing any substantial agglomeration of the same.
One object of the present invention is to provide a method for fabricating CMOS structures in which at least one metal silicide contact is formed prior to activating the source/drain regions of the structure.
Another object of the present invention is to provide a method of fabricating a CMOS structure that contains metal silicide contacts which exhibit little or no agglomeration upon high temperature annealing.
A further object of the present invention is to provide a method of fabricating metal silicide contacts that have increased high temperature stability, yet have a resistivity value that is within current operational standards.
A still further object of the present invention is to provide a metal silicide contact that exists in its lowest resistance phase. For example, when a cobalt (Co) silicide contact is desired, the present invention forms the Co disilicide phase; and when a titanium (Ti) contact is desired, the present invention forms the C54 phase of TiSi2. Both of the above mentioned phases, i.e., Co disilicide and C54 phase of TiSi2, represent the lowest resistance phase of the metal. That is, the Co disilicide phase is of lower resistance than the Co monosilicide phase, while the C54 phase of TiSi2 is of lower resistance than the C49 phase of TiSi2. It is noted that the higher resistance silicide phase material is highly resistance to etching, i.e., substantially non-ecthable, in the etchant solutions mentioned hereinbelow. That is, the higher resistance silicide phase material is substantially non-etchable compared to the unreacted metal alloy layer.
These and other objects and advantages can be obtained in the present invention by adding at least one alloying element to a metal which is capable of producing a metal silicide upon annealing prior to activation of source/drain regions in the structure. By alloying the metal prior to the high temperature source/drain activation anneal, the metal alloy silicide contact of the present invention does not agglomerate. Specifically, the method of the present invention comprises the steps of:
(a) forming a metal alloy layer over a portion of a silicon-containing substrate, said metal alloy layer comprising Co or Ti and an alloying additive, said silicon-containing layer not containing activated source/drain regions embedded therein;
(b) annealing said metal alloy layer at a temperature which is effective in converting a portion of said metal alloy layer into a metal alloy silicide layer that is highly resistant to etching as compared to the unreacted metal alloy layer;
(c) removing any remaining metal alloy layer not converted in step (b);
(d) optionally, annealing said metal alloy silicide layer produced in step (b) so as to convert the same into its lowest resistant phase; and
(e) forming activated source/drain regions in said silicon-containing substrate by at least annealing at a temperature of about 900xc2x0 C. or above, whereby the metal alloy silicide layer formed in steps (b) or (d) does not agglomerate during said activation annealing, and is in its lowest resistance phase after said activation annealing.
Another aspect of the present invention relates to CMOS structures containing the inventive non-agglomerated metal silicide contacts. Specifically, the CMOS structures of the present invention comprise:
a substrate having an exposed region of a silicon-containing semiconductor material, said silicon-containing semiconductor material having source/drain regions formed therein; and
a substantially non-agglomerated metal alloy silicide contact formed on a portion of said silicon-containing semiconductor substrate, wherein said substantially non-agglomerated metal alloy silicide contact withstands high temperature annealing conditions which are employed in fabricating the source/drain regions and is in its lowest resistance phase, said source/drain regions being formed after the metal alloy silicide contact is formed.